Published Papers Archive

Direct digital synthesis (DDS) is a fundamental build- ing block for generating precise, agile sinusoidal wave- forms in modern communication, radar, instrumentation, and signal-processing systems. Over several decades, a wide range of phase-to-amplitude conversion architec- tures have been developed to address the central design trade-off in DDS: achieving high spectral purity and fre- quency resolution while minimizing memory, arithmetic, and power overhead. The architectures are organized into lookup-table (LUT) based, coordinate rotation digital computer (CORDIC) based, polynomial-approximation (Taylor, Chebyshev/minimax, and piecewise-polynomial) based, and recursive difference-equation based architec- tures, along with hybrid combinations (LUT–CORDIC, LUT–Taylor) and multiplier-based trigonometric synthe- sis that relocate the memory/arithmetic trade-off across these core approaches. The theoretical foundations, gov- erning equations, and hardware implications of each tech- nique are discussed, including quantitative error-bound analysis for Taylor-series truncation and range reduction. Complementary noise-shaping and spur-reduction tech- niques including delta-sigma modulation, phase and am- plitude dithering, and stochastic quantization are dis- cussed. DAC-less output-stage approaches such as pulse- width modulation, are also reviewed. Standard perfor- mance metrics are formalized to characterize the quality of DDS output. A qualitative comparison of all discussed techniques is provided offering designers a consolidated reference for selecting an appropriate DDS architecture.

The automotive electrical/electronic (E/E) architecture is undergoing a fundamental transformation from loosely coupled, function-specific electronic control units (ECUs) toward domain-centralized, zonal, and fully centralized computing architectures, forming the foundation of emerg- ing software-defined vehicles (SDVs). In parallel, artifi- cial intelligence (AI) and machine learning (ML) are mov- ing from predominantly cloud-based analytics toward di- rect deployment within automotive ECUs, enabling per- ception, prediction, diagnosis, cybersecurity, and adaptive control on resource-constrained embedded platforms. This paper presents a structured literature review of AI/ML- enabled ECU design within the SDV paradigm. It first introduces ECU fundamentals, functional roles, and in- vehicle networking, including a representative zonal SDV architecture integrating controller area network (CAN), CAN with flexible data-rate (CAN-FD), local intercon- nect network (LIN), and automotive Ethernet. The evolution from distributed to domain, zonal, and cen- tralized architectures is then discussed. Major ECU categories, including powertrain, transmission and en- ergy management, battery management systems (BMSs), chassis and safety, advanced driver assistance systems (ADAS) and autonomous driving, body control, infotain- ment and connectivity, and gateway, zonal, and central- compute ECUs, are systematically reviewed using func- tional diagrams, AI/ML techniques, datasets, and rele- vant literature. The paper also examines AI/ML train- ing, optimization, compression, validation, and deploy- ment on automotive system-on-chips (SoCs), with em- phasis on the automotive open system architecture (AU- TOSAR) adaptive platform, edge-AI accelerators, over- the-air (OTA) updates, field-programmable gate array (FPGA)-accelerated inference, and application-specific in- tegrated circuit (ASIC)-based implementations. Finally, key challenges in functional safety, real-time determin- ism, explainability, resource constraints, cybersecurity, and reliable software updates are discussed, followed by future research directions for efficient and hardware-aware AI/ML integration in SDV-oriented ECU architectures.

Activation functions (AFs) are fundamental components of neural networks (NNs), introducing nonlinearity that enables models to learn complex representations and decision boundaries. With the growing adoption of NNs in real-time and embedded systems, there is an increasing demand for efficient hardware implementations. Implementing AFs on hardware poses significant challenges due to the presence of nonlinear operations and transcendental functions, especially exponential computations required by commonly used AFs such as sigmoid, hyperbolic tangent, and softmax. Efficient approximation and computation techniques for exponential functions (EFs) are essential to enable practical and high-performance hardware realizations of AFs. This paper presents a comprehensive survey of techniques for implementing AFs on digital hardware. The contributions include a concise review of widely used and emerging AFs, a survey of major EF computation methods such as lookup tables, polynomial and piecewise approximations, COordinate Rotation DIgital Compute (CORDIC) based approaches, and iterative algorithms, and a detailed examination of hardware-oriented implementation strategies for AFs. The surveyed techniques are analyzed in terms of accuracy, resource utilization, latency, and power efficiency. This survey aims to provide valuable insights and design guidelines for researchers and practitioners developing efficient NN accelerators on field gate programmable array (FPGA) and other digital hardware platforms.

Artificial intelligence and machine learning (AI-ML) al- gorithms gave a new direction to the problem of image classification. All practical applications are nowadays ap- plying AI-ML algorithms for image classification. Con- volutional neural network (CNN) and its varieties rapidly became researcher’s first choice for computer vision related applications. Recently many implementations of hard- ware accelerators for CNN are reported in literature. The current work exploits the opportunities for improvements and proposes a novel very large scale integrated circuit (VLSI) architecture for classic CNN model for classifica- tion of gray-scale images. The proposed architecture is validated using field gate programmable array (FPGA) platform for classification of handwritten digits and hand gestures. The architecture is implemented on both Artix7 and Zynq FPGA board. This work achieves 96% classifi- cation accuracy for digits detection and 97% accuracy for gesture images using same CNN model with pre-defined filters in the convolution stage. Proposed architecture consumes less hardware resources compared to state-of- the-art works by using a single vector multiplication unit (VMU) for both convolution-pooling stage and fully con- nected network. Architecture supports parallel convolu- tion and pooling operation and achieves processing speed of ≈16 μs per image frame of size 28 × 28. Also, the archi- tecture is scalable and supports deep learning where more number of convolution-pooling stages may be used.